1. Field of the Invention
The present invention relates to a high frequency switch and an electronic device including the same, and more particularly to a high frequency switch for switching a signal especially in an extremely high frequency band and an electronic device including the same.
2. Description of the Related Art
Generally, switches containing PIN diodes are used for the change-over of signals in an extremely high frequency band. Moreover, switches using an FET are used for signals in a relatively low frequency region in the extremely high frequency band. Especially, there are used switches utilizing lines through which high frequency signals are transmitted, as the drains and the sources of the FET. Such switches are specifically disclosed in Japanese Unexamined Patent Application Publication Nos. 6-232601 (Patent Document 1), 10-41404 (Patent Document 2), 2000-294568 (Patent Document 3), and 2000-332502 (Patent Document 4).
As disclosed in Patent Document 1, a signal line is separated by plural slits which cross the signal line in the width direction to form plural drain electrodes. Source electrodes and gate electrodes (lines) are formed, which extend in the width direction of the signal line similarly to the slits. Thus, the high frequency switch uses a part of the signal line as an FET (e.g., see FIG. 13 of Patent Document 1). The respective drain electrodes are connected to each other with metallic wirings. An inductance element is connected between the drain and the source of the FET, which parallel-resonates with the off-capacitor of the FET at a signal frequency.
Referring to Patent Document 1, the signal line itself, including the part thereof where the FET is formed, is always in the DC conduction state. When the FET is on, the impedance of the circuit connected between the signal line and the ground becomes small, causing substantially the short-circuited state. As a result, a part of the signal line is substantially grounded, so that a high frequency signal is reflected, and thus, the conduction is blocked. On the other hand, when the FET is off, the impedance at the frequency of the high frequency signal of the circuit connected between the signal line and the ground becomes infinite, due to the parallel resonance of the off-capacitor of the FET and the inductance element. This means that equivalently, nothing is connected to the signal line at the frequency of the high frequency signal. Thus, the high frequency signal is transmitted and the switching operation is carried out.
Patent Document 2 discloses a high frequency switch in which a ground electrode (which functions as a source electrode) is formed adjacently to a part of a signal line (which functions as a drain electrode) so as to extend in the longitudinal directional of the signal line, and a gate electrode is formed in the gap between the signal line and the gate electrode so as to extend in the longitudinal direction of the signal line (e.g., see FIG. 6 in Patent Document 1).
In the high frequency switch disclosed in Patent Document 2, when the FET is off, the part of the signal line which has a function as a drain simply operates as a signal line. Thus, a high frequency signal is transmitted through the signal line. On the other hand, when the FET is on, the part of the signal which has a function as a drain is connected to the ground electrode. Hence, the part of the signal line is substantially grounded, so that the high frequency signal is reflected, and the conduction is blocked.
Patent Document 3 discloses a configuration which is similar to the PET configuration of Patent Document 1 (e.g., see FIG. 3 of Patent Document 3, where no inductance element for parallel resonance is provided). In the configuration of Patent Document 3, the drain, the source, and the gate of the FET are formed so as to extend in the line direction of the signal line (see FIG. 1 of Patent Document 3).
The operation of the high frequency switch disclosed in Patent Document 3 is the same as that of the high frequency switch of Patent Document 2 in that when the FET is on, the part of the signal line is substantially grounded, so that the propagation of the high frequency signal is blocked.
As disclosed in Patent Document 4, a one-fourth wavelength stub is connected to the main line of a signal line, the top portion of the stub functions as a drain electrode, and the source electrode is grounded. Thus, the FET is formed (see FIGS. 2 and 6 of Patent Document 4). By turning the FET on-off, the stub is caused to function as a short stub or an open stub.
The operation of the high frequency switch disclosed in Patent Document 4 is the same as that of the high frequency switches of Patent Documents 2 and 3 in that when the FET is off, the stub functions as a one-fourth open stub, so that a part of the signal line is substantially grounded at the frequency of a high frequency signal, whereby the propagation of the high frequency signal is blocked.
Referring to Patent Document 1, the conduction resistance caused when the FET is on is required to be small. For this purpose, it is necessary to increase the splitting number for the signal line so that the number of gate electrodes increases, and the total gate width of the FET becomes large. When the total gate width is increased, inevitably, the off-capacitor of the FET becomes large. Therefore, it is necessary to reduce the inductance of the inductance element for parallel resonance. However, reducing the size of the inductance element while the accuracy of the inductance is kept has a limitation. When the signal frequency becomes higher, the inductance is required to be smaller. Thus, problematically, it is more difficult to use the configuration at a higher signal frequency.
On the other hand, according to Patent Document 2, the high frequency switch utilizes no resonance phenomenon. Thus, the above-described problem in that the use of the high frequency switch becomes difficult at a higher signal frequency does not occur. However, according to the high frequency switch of Patent Document 2, the main line of the signal line through which a high frequency signal flows when the switch is on functions as the drain electrode of FET. At least a part of the drain electrode is formed on a semiconductor activation layer. That is, a part of the mainline is formed on the semiconductor activation layer. The semiconductor activation layer is a conductor having a higher resistance than the drain electrode. Thus, this means that the resistance of the main line becomes large. Accordingly, in the high frequency switch in which the main line functions as the drain electrode of FET as disclosed in Patent Document 1, problematically, the function of the main line as the drain electrode causes the insertion loss of the main line to increase.
The on-resistance per unit length of the FET (per unit gate-width) can be changed by modifying the sectional-configuration of the FET. However, it is difficult to carry out the modification. In the case in which the on-resistance per unit length can not be changed, it is necessary to increase the gate width of the FET to sufficiently ground the main line electrode when the FET is on. Increasing of the gate width of the FET means that the gate electrode is extended in the longitudinal direction of the signal line. Thus, the length of the drain electrode increases. This means that the size of the switch increases in the longitudinal direction of the main line. The drain electrode is composed of the main line electrode through which a high frequency signal flows, the main line electrode being formed on the semiconductor activation layer. Therefore, the insertion loss of the main line electrode as described above will be further increased.
The high frequency switch disclosed in Patent Document 3 has the same basic configuration as that of the high frequency switch of Patent Document 1. Thus, similar problems occur.
Referring to the high frequency switch disclosed in Patent Document 4, the main line through which a high frequency signal flows does not function as a drain electrode. Thus, the problem in that the insertion loss when the switch is on increases does not occur. However, for the purpose of grounding the end of the stub at a satisfactorily low resistance, it is necessary to sufficiently increase the gate width. When the gate width of the FET is increased, the capacitance between the drain and the source, caused when the FET is off, increases. This means that a large capacitance is produced between the top of the open stub and the ground when the FET is off. When the large capacitance is present at the top of the open stub, the resonance frequency of the open stub is reduced. Thus, most probably, it will differ from the resonance frequency of the short stub. Since the resonance frequencies of the open stub line electrode and the short stub line electrode can not be set to be equal to each other, the high frequency switch can not properly function as a switch. These problems are to be solved.